MARC details
| 000 -LEADER |
| fixed length control field |
01786cam a2200349 i 4500 |
| 001 - CONTROL NUMBER |
| control field |
15141403 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
| control field |
20210222113421.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
| fixed length control field |
080114s2018 ii a 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
| LC control number |
2008001634 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
| International Standard Book Number |
9780198093299 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
| International Standard Book Number |
0198093292 |
| 040 ## - CATALOGING SOURCE |
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
UKM |
| -- |
BTCTA |
| -- |
YDXCP |
| -- |
BAKER |
| -- |
BWX |
| -- |
COD |
| -- |
IXA |
| -- |
DLC |
| Description conventions |
rda |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
| Classification number |
TK7888.4 |
| Item number |
.B76 2008 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
| Classification number |
621.395 |
| Edition number |
23 |
| Item number |
D.D.V |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
| Personal name |
Das, Debaprasad. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
| Title |
VHDL : |
| Remainder of title |
design, synthesis, and simulation / |
| Statement of responsibility, etc |
Debaprasad Das. |
| 264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
| Place of publication, distribution, etc |
New Delhi : |
| Name of publisher, distributor, etc |
Oxford University Press, |
| Date of publication, distribution, etc |
[2018] |
| 264 #4 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
| Date of publication, distribution, etc |
©2018 |
| 300 ## - PHYSICAL DESCRIPTION |
| Extent |
xviii, 588 pages : |
| Other physical details |
illustrations ; |
| Dimensions |
22 cm |
| 336 ## - CONTENT TYPE |
| Source |
rdacontent |
| Content type term |
text |
| 337 ## - MEDIA TYPE |
| Source |
rdamedia |
| Media type term |
unmediated |
| 338 ## - CARRIER TYPE |
| Source |
rdacarrier |
| Carrier type term |
volume |
| 500 ## - GENERAL NOTE |
| General note |
Includes index. |
| 505 0# - FORMATTED CONTENTS NOTE |
| Formatted contents note |
Introduction to Digital Logic Design<br/>Introduction to VHDL -- Dataflow Modeling -- Behavioral Modeling -- Structural Modeling -- Mixed Modeling -- Concurrent Statements -- Sequential Statements -- Advanced VHDL -- Arithmetic Logic Unit Design -- Model Simulation -- Delay Modeling -- Verification and Testing -- Synthesis -- Place and Route -- File I/O -- Floating-point Arithmetic -- Design with FPGA and CPLD -- Memories and Buses -- Design Examples -- Introduction to Verilog |
| 538 ## - SYSTEM DETAILS NOTE |
| System details note |
Minimum system requirements (PC): Pentium III processor or later; Windows XP or later; USB port for connecting a USB-Blaster; TCP/IP networking protocol installed; Internet Explorer 6.0 or later. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
| Topical term or geographic name as entry element |
Logic circuits |
| General subdivision |
Design and construction |
| -- |
Data processing. |
| 9 (RLIN) |
26019 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
| Topical term or geographic name as entry element |
Logic design |
| General subdivision |
Data processing. |
| 9 (RLIN) |
26020 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
| Topical term or geographic name as entry element |
VHDL (Computer hardware description language) |
| 9 (RLIN) |
26021 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
| Koha item type |
Books |
| Source of classification or shelving scheme |
Dewey Decimal Classification |