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Principles of digital design / (Record no. 2413)

MARC details
000 -LEADER
fixed length control field	03775nam a2200325 i 4500
001 - CONTROL NUMBER
control field	2104586
005 - DATE AND TIME OF LATEST TRANSACTION
control field	20210222115045.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field	960118s1997 njua f b 001 0 eng d
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number	96001339
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number	0133011445
040 ## - CATALOGING SOURCE
Original cataloging agency	DLC
Transcribing agency	DLC
Modifying agency	DLC
Description conventions	rda
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number	621.395
Edition number	20
Item number	G.D.P.
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name	Gajski, Daniel D.
9 (RLIN)	9947
Relator term	author.
245 10 - TITLE STATEMENT
Title	Principles of digital design /
Statement of responsibility, etc	Daniel D. Gajski.
264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc	Upper Saddle River, N.J. :
Name of publisher, distributor, etc	Prentice Hall,
Date of publication, distribution, etc	[1997]
264 #4 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Date of publication, distribution, etc	©1997
300 ## - PHYSICAL DESCRIPTION
Extent	xv, 447 pages :
Other physical details	illustrations (some color) ;
Dimensions	24 cm
336 ## - CONTENT TYPE
Source	rdacontent
Content type term	text
337 ## - MEDIA TYPE
Source	rdamedia
Media type term	unmediated
338 ## - CARRIER TYPE
Source	rdacarrier
Carrier type term	volume
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc	Includes bibliographical references and index.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note	1.Introduction -- Design representation -- Levels of abstraction -- Design process -- CAD tools -- Typical design process -- Road map – 2. Data Types and Representations -- Positional number systems -- Octal and hexadecimal numbers -- Number system conversions -- Addition and subtraction of binary numbers -- Representation of negative numbers -- Two's-complement addition and subtraction -- Binary ultiplication -- Binary division -- Floating-point number representation -- Binary codes for decimal numbers -- Character codes -- Codes for error detection and correction -- Hamming codes – 3. Boolean Algebra and Logic Design -- Algebraic properties -- Axiomatic definition of boolean algebra -- Basic theorems of boolean algebra -- Boolean functions -- Canonical forms -- Standard forms -- Digital logic gates -- Extension to multiple inputs and multiple operators -- Gate implementations -- VLSI technology – 4. Simplification of Boolean Functions -- The map representation -- The map method of simplification -- Don't-care conditions -- The tabulation method -- Technology mapping for gate arrays -- Technology mapping for custom libraries -- Hazard-free design – 5. Combinatorial Components -- Carry-ripple adders -- Carry-look-ahead adders -- Adders/subtractors -- Logic unit -- Arithmetic-Logic Unit -- Decoders -- Selectors -- Buses -- Priority encoders -- Magnitude comparators -- Shifters and rotators -- Read-Only memories -- Programmable logic arrays – 6. Sequential Logic -- SR-latch -- Gated SR-latch -- Gated D-latch -- Flip-flops -- Flip-flop types -- Analysis of sequential logic -- Finite-state-machine model -- Synthesis of sequential logic -- FSM model capture -- State minimization -- State encoding -- Choice of memory elements -- Optimization and timing – 7. Storage Components -- Registers -- Shift registers -- Counters -- BCD counter -- Asynchronous counter -- Register files -- Random-access memories (RAMs) -- Push-down stacks -- Firs- in-first-out queue -- Simple datapaths -- General datapaths -- Control unit design – 8. Register-Transfer Design -- Design model -- FSMD definition -- Algorithmic-state-machine charts -- Synthesis from ASM charts -- Register sharing (variable merging) -- Functional unit sharing (operator sharing) -- Bus sharing (connection merging) -- Register merging -- Chaining and multicycling -- Functional unit pipelining -- ASM pipelining -- Control- pipelining -- Scheduling – 9.Processor Design -- Instruction sets -- Addressing modes -- Processor design -- Instruction set design -- Processor design -- Reduced instruction set -- RISC Design -- Data forwarding -- Branch prediction.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element	Integrated circuits
General subdivision	Design
--	Data processing.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element	Logic design
General subdivision	Data processing.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element	Computer-aided design.
906 ## - LOCAL DATA ELEMENT F, LDF (RLIN)
a	7
b	cbc
c	orignew
d	1
e	ocip
f	19
g	y-gencatlg
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme	Dewey Decimal Classification
Koha item type	Books

Holdings
Lost status	Source of classification or shelving scheme	Damaged status	Not for loan	Collection code	Home library	Current library	Shelving location	Date acquired	Cost, normal purchase price	Inventory number	Total Checkouts	Full call number	Barcode	Date last seen	Price effective from	Koha item type	Source of acquisition
	Dewey Decimal Classification			Faculty of Engineering & Technology (Electrical)	Main library	Main library	B3	22/05/2007	30.00	PU		621.395 G.D.P.	00004605	19/02/2025	21/09/2010	Books
	Dewey Decimal Classification			Faculty of Engineering & Technology (Electrical)	Main library	Main library	B3	15/03/2009	30.00	PU		621.395 G.D.P.	00003710	19/02/2025	21/09/2010	Books	American university