MARC details
| 000 -LEADER |
|---|
| fixed length control field |
03432nam a2200361 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
1198780 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20210926104849.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
980609t19981999maua f 001 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
98028075 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0072925078 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
DLC |
| Description conventions |
rda |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
21 |
| Item number |
K.S.C. |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Kang, Sung-Mo, |
| Dates associated with a name |
1945-, |
| 9 (RLIN) |
9951 |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
CMOS digital integrated circuits : |
| Remainder of title |
analysis and design / |
| Statement of responsibility, etc |
Sung-Mo (Steve) Kang, Yusuf Leblebici. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
Second edition |
| 264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Boston, MA : |
| Name of publisher, distributor, etc |
McGraw-Hill, |
| Date of publication, distribution, etc |
[1998] |
| 264 #4 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Date of publication, distribution, etc |
©1999 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xv, 658 pages : |
| Other physical details |
illustrations ; |
| Dimensions |
25 cm |
| 336 ## - CONTENT TYPE |
|---|
| Source |
rdacontent |
| Content type term |
text |
| 337 ## - MEDIA TYPE |
|---|
| Source |
rdamedia |
| Media type term |
unmediated |
| 338 ## - CARRIER TYPE |
|---|
| Source |
rdacarrier |
| Carrier type term |
volume |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
ch. 1 Introduction -- 1.1. Historical Perspective -- 1.2. Objective and Organization of the Book -- 1.3. A Circuit Design Example -- ch. 2 Fabrication of MOSFETs -- 2.1. Introduction -- 2.2. Fabrication Process Flow: Basic Steps -- 2.3. The CMOS n-Well Process -- 2.4. Layout Design Rules -- 2.5. Full-Custom Layout Design Rules -- ch. 3 MOS Transistor -- 3.1. The Metal Oxide Semiconductor (MOS) Structure -- 3.2. The MOS System Under External Bias -- 3.3. Structure and Operation of the MOS Transistor (MOSFET) -- 3.4. MOSFET Current-Voltage Characteristics -- 3.5. MOSFET Scaling and Small-Geometry Effects -- 3.6. MOSFET Capacitances -- ch. 4 Modelling of MOS Transistors Using SPICE -- 4.1. Basic Concepts -- 4.2. The Level 1 Model Equations -- 4.3. The Level 2 Model Equations -- 4.4. The Level 3 Model Equations -- 4.5. Capacitance Models -- 4.6. Comparison of the SPICE MOSFET Models -- ch. 5 MOS Inverters: Static Characteristics -- 5.1. Introduction -- 5.2. Resistive-Load Inverter -- 5.3. Inverters with MOSFET Load -- 5.4. CMOS Inverter -- ch. 6 MOS Inverters: Switching Characteristics and Interconnect Effects -- 6.1. Introduction -- 6.2. Delay-Time Definitions --6.3. Calculation of Delay Times -- 6.4. Inverter Design with Delay Constraints -- 6.5. Estimation of Interconnect Parasitics -- 6.6. Calculation of Interconnect Delay -- 6.7. Switching Power Dissipation of CMOS Inverters -- ch. 7 Combinational MOS Logic Circuits -- 7.1. Introduction -- 7.2. MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads -- 7.3. CMOS Logic Circuits -- 7.4. Complex Logic Circuits -- 7.5. CMOS Transmission Gates (Pass Gates) -- ch. 8 Sequential MOS Logic Circuits --<br/>8.1. Introduction -- 8.2. Behaviour of Bistable Elements -- 8.3. The SR Latch Circuit -- 8.4. Clocked Latch and Flip-Flop Circuits -- 8.5. CMOS D-Latch and Edge-Triggered Flip-Hop -- ch. 9 Dynamic Logic Circuits -- 9.1. Introduction --<br/>9.2. Basic Principles of Pass Transistor Circuits -- 9.3. Voltage Bootstrapping -- 9.4. Synchronous Dynamic Circuit Techniques -- 9.6. High-Performance Dynamic CMOS Circuits -- <br/> |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Metal oxide semiconductors, Complementary. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Digital integrated circuits. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Leblebici, Yusuf. |
| 9 (RLIN) |
9954 |
| Relator term |
author. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Publisher description |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/description/mh023/98028075.html">http://www.loc.gov/catdir/description/mh023/98028075.html</a> |
| 856 41 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Table of contents |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/toc/mh022/98028075.html">http://www.loc.gov/catdir/toc/mh022/98028075.html</a> |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ocip |
| f |
19 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |