MARC details
| 000 -LEADER |
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| fixed length control field |
04898cam a2200373 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
15661354 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200928153838.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
090316s2009 ne a b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
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| LC control number |
2009011196 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780123742308 (hardcover : alk. paper) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
0123742307 (hardcover : alk. paper) |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
BTCTA |
| -- |
YDXCP |
| -- |
UKM |
| -- |
C#P |
| -- |
BWX |
| -- |
CDX |
| -- |
DLC |
| -- |
EG-NcFUE |
| Description conventions |
rda |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7895.E42 |
| Item number |
R72 2009 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
004.1 |
| Item number |
R.A.E |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Roychoudhury, Abhik. |
| 245 10 - TITLE STATEMENT |
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| Title |
Embedded systems and software validation / |
| Statement of responsibility, etc |
Abhik Roychoudhury. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Place of publication, distribution, etc |
Amsterdam ; |
| -- |
Boston : |
| Name of publisher, distributor, etc |
Morgan Kaufmann Publishers/Elsevier, |
| Date of publication, distribution, etc |
c2009. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
xii, 254 pages. : |
| Other physical details |
illustration ; |
| Dimensions |
25 cm. |
| 336 ## - CONTENT TYPE |
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| Source |
rdacontent |
| Content type term |
text |
| 337 ## - MEDIA TYPE |
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| Source |
rdamedia |
| Media type term |
unmediated |
| 338 ## - CARRIER TYPE |
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| Source |
rdacarrier |
| Carrier type term |
volume |
| 490 1# - SERIES STATEMENT |
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| Series statement |
The Morgan Kaufmann series in systems on silicon |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc |
Includes bibliographical references (p. 233-239) and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
1 Introduction<br/><br/>2 Model Validation<br/>2.1 Platform vs System Behavior<br/>2.2 Criteria for Design Model<br/>2.3 Informal Requirements: A Case Study<br/>2.3.1 The Requirements Document<br/>2.3.2 Simplication of the Informal Requirements<br/>2.4 Common Modeling Notations<br/>2.4.1 Finite State Machines (FSM)<br/>2.4.2 Communicating FSMs<br/>2.4.3 Message Sequence Chart based Models<br/>2.5 Remarks about Modeling Notations<br/>2.6 Model Simulations<br/>2.6.1 FSM simulations<br/>2.6.2 Simulating MSC-based System Models<br/>2.7 Model-based Testing<br/>2.8 Model Checking<br/>2.8.1 Property Specifcation<br/>2.8.2 Checking procedure<br/>2.9 The SPIN Validation Tool<br/>2.10 The SMV Validation Tool<br/>2.11 Case Study: Air Traffic Controller<br/>2.12 References<br/>2.13 Exercises<br/><br/>3 Communication Validation<br/>3.1 Common Incompatibilities<br/>3.1.1 Sending/receiving signals in di erent order<br/>3.1.2 Handling a diffrent signal alphabet<br/>3.1.3 Mismatch in data format<br/>3.1.4 Mismatch in data rates<br/>3.2 Converter Synthesis<br/>3.2.1 Representing Native Protocols and Converters<br/>3.2.2 Basic ideas for Converter synthesis<br/>3.2.3 Various strategies for protocol conversion<br/>3.2.4 Avoiding no-progress cycles<br/>3.2.5 Speculative transmission to avoid deadlocks<br/>3.3 Changing a working design<br/>3.4 References<br/>3.5 Exercises<br/><br/>4 Performance Validation<br/>4.1 The Conventional Abstraction of Time<br/>4.2 Predicting Execution Time of a Program<br/>4.2.1 WCET Calculation<br/>4.2.2 Modeling of Micro-architecture<br/>4.3 Interference within a Processing Element<br/>4.3.1 Interrupts from Environment<br/>4.3.2 Contention and Preemption<br/>4.3.3 Sharing a Processor Cache<br/>4.4 System level communication analysis<br/>4.5 Designing Systems with Predictable Timing<br/>4.5.1 Scratchpad Memories<br/>4.5.2 Time-triggered Communication<br/>4.6 Emerging applications<br/>4.7 References<br/>4.8 Exercises<br/><br/>5 Functionality Validation<br/>5.1 Dynamic or Trace-based Checking<br/>5.1.1 Dynamic Slicing<br/>5.1.2 Fault Localization<br/>5.1.3 Directed Testing Methods<br/>5.2 Formal Verifcation<br/>5.2.1 Predicate Abstraction<br/>5.2.2 Software Checking via Predicate Abstraction<br/>5.2.3 Combining Formal Verifcation with Testing<br/>5.3 References<br/>5.4 Exercises |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
Modern embedded systems require high performance, low cost and low power consumption. Such systems typically consist of a heterogeneous collection of processors, specialized memory subsystems, and partially programmable or fixed-function components. This heterogeneity, coupled with issues such as hardware/software partitioning, mapping, scheduling, etc., leads to a large number of design possibilities, making performance debugging and validation of such systems a difficult problem.<br/>Embedded systems are used to control safety critical applications such as flight control, automotive electronics and healthcare monitoring. Clearly, developing reliable software/systems for such applications is of utmost importance. This book describes a host of debugging and verification methods which can help to achieve this goal.<br/>• Covers the major abstraction levels of embedded systems design, starting from software analysis and micro-architectural modeling, to modeling of resource sharing and communication at the system level<br/>• Integrates formal techniques of validation for hardware/software with debugging and validation of embedded system design flows<br/>• Includes practical case studies to answer the questions: does a design meet its requirements, if not, then which parts of the system are responsible for the violation, and once they are identified, then how should the design be suitably modified?<br/> |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Embedded computer systems |
| General subdivision |
Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Embedded computer systems |
| General subdivision |
Testing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Computer software |
| General subdivision |
Testing. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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| Uniform title |
Morgan Kaufmann series in systems on silicon. |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
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| Materials specified |
Abstract |
| Uniform Resource Identifier |
<a href="http://repository.fue.edu.eg/xmlui/handle/123456789/3496">http://repository.fue.edu.eg/xmlui/handle/123456789/3496</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Books |
| Source of classification or shelving scheme |
Dewey Decimal Classification |