MARC details
| 000 -LEADER |
|---|
| fixed length control field |
04046cam a2200385 i 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
18399488 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20210222113146.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
141208s2016 maua 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2014047146 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781292096070 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
1292096071 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Language of cataloging |
eng |
| Transcribing agency |
DLC |
| Description conventions |
rda |
| Modifying agency |
DLC |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7888.4 |
| Item number |
.M36 2016 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.392 |
| Edition number |
22 |
| Item number |
M.M.L |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mano, M. Morris, |
| Dates associated with a name |
1927-, |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Logic and computer design fundamentals / |
| Statement of responsibility, etc |
M. Morris Mano, California State University, Los Angeles, Charles R. Kime, University of Wisconsin, Madison, Tom Martin, Virginia Tech. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
Fifth edition |
| 264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Boston : |
| Name of publisher, distributor, etc |
Pearson, |
| Date of publication, distribution, etc |
[2016] |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvi, 656 pages: |
| Other physical details |
illustrations ; |
| Dimensions |
25 cm |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
unmediated |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
volume |
| Source |
rdacarrier |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Includes index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Digital Systems and Information -- 1-1 Information Representation -- 1-2 Abstraction Layers in Computer Systems Design -- 1-3 Number Systems -- 1-4 Arithmetic Operations -- 1-5 Decimal Codes -- 1-6 Alphanumeric Codes -- 1-7 Gray Codes -- 1-8 Chapter Summary -- 2. Combinational Logic Circuits -- 2-1 Binary Logic and Gates -- 2-2 Boolean Algebra -- 2-3 Standard Forms -- 2-4 Two-Level Circuit Optimization -- 2-5 Map Manipulation -- 2-6 Exclusive-OR Operator and Gates -- 2-7 Gate Propagation Delay -- 2-8 Hardware Description Languages Overview -- 2-9 HDL Representations-VHDL -- 2-10 HDL Represenations-Verilog -- 2-11 Chapter Summary -- 3. Combinational Logic Design -- 3-1 Beginning Hierarchical Design -- 3-2 Technology Mapping -- 3-3 Combinational Functional Blocks -- 3-4 Rudimentary Logic Functions -- 3-5 Decoding -- 3-6 Encoding -- 3-7 Selecting -- 3-8 Iterative Combinational Circuits -- 3-9 Binary Adders -- 3-10 Binary Subtraction -- 3-11 Binary Adder-Subtractors -- 3-12 Other Arithmetic Functions -- 3-13 Chapter Summary -- 4. Sequential Circuits -- 4-1 Sequential Circuit Definitions -- 4-2 Latches -- 4-3 Flip-Flops -- 4-4 Sequential Circuit Analysis -- 4-5 Sequential Circuit Design -- 4-6 State-machine Diagrams and Applications -- 4-7 HDL Representation for Sequential Circuits-VHDL -- 4-8 HDL Representation for Sequential Circuits-Verilog -- 4-9 Flip-Flop Timing -- 4-10 Sequential Circuit Timing -- 4-11 Asynchronous Interactions -- 4-12 Synchronization and Metastability -- 4-13 Synchronous Circuit Pitfalls -- 4-14 Chapter Summary -- 5. Digital Hardware Implementation -- 5-1 The Design Space -- 5-2 Programmable Implementation Technologies -- 5-3 Chapter Summary -- 6. Registers and Register Transfers -- 6-1 Registers and Load Enable -- 6-2 Register Transfers -- 6-3 Register Transfer Operations -- 6-4 Register Transfers in VHDL and Verilog -- 6-5 Microoperations -- 6-6 Microoperations on a Single Register -- 6-7 Register-Cell Design -- 6-8 Multiplexer and Bus-Baed Transfers for Multiple Registers -- 6-9 Serial Transfer and Microoperations -- 6-10 Control of Register Transfers -- 6-11 HDL Representation for Shift Registers and Counters-VHDL -- 6-12 HDL Representation for Shift Registers and Counters Verilog -- 6-13 Microprogrammed Control -- 6-15 Chapter Summary -- 7. Memory Basics -- 7-1 Memory Definitions -- 7-2 Random-Access Memory -- 7-3 SRAM Integrated Circuits -- 7-4 Array of SRAM ICs -- 7-5 DRAM ICs -- 7-6 DRAM Types -- 7-7 Arrays of Dynamic RAM ICs -- 7-8 Chapter Summary -- 8. Computer Design Basics -- 8-1 Computer Design Basics -- 8-2 Datapaths -- 8-3 The Arithmetic/Logic Unit -- 8-4 The Shifter |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Electronic digital computers |
| General subdivision |
Circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Logic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Logic design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Kime, Charles R. |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Martin, Tom, |
| Dates associated with a name |
1969-, |
| Relator term |
author. |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ecip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |