Microwave power amplifier design with MMIC modules / Howard Hausman.

Minimal Level Cataloging Plus. DLC

Includes bibliographical references and index.

Machine generated contents note: 1.1.Introduction to Designing Microwave Solid State Power Amplifiers -- 1.2.Applications of SSPAs -- 1.3.A Typical SSPA Configuration -- 1.4.Typical Documents Starting a Project -- 1.5.General Format of the SCD -- 1.5.1.Paragraph 1.0: Scope -- 1.5.2.Paragraph 2.0: Applicable Documents -- 1.5.3.Paragraph 3.0: Requirements -- 1.5.4.Paragraph 4.0: Verification -- 1.5.5.Paragraph 5.0: Packaging -- 1.5.6.Paragraph 6.0: Notes -- 1.6.Requirements Section of an SCD -- 1.6.1.Electrical Requirements -- 1.6.2.Mechanical Requirements -- 1.6.3.Environmental Requirements -- 1.6.4.Other Design Criteria -- References -- ch. 2 Lumped Components in RF and Microwave Circuitry -- 2.1.Applicability of Lumped Element Analysis -- 2.1.1.Calculating Wavelengths -- 2.1.2.Example: Calculating Wavelengths for Lumped Circuit Analysis -- 2.2.Capacitor Characteristics at High Frequencies -- 2.2.1.Single-Layer and Multilayer Capacitor Construction

Note continued: 2.2.2.High-Frequency Capacitor Models -- 2.2.3.Capacitor Losses (Q) -- 2.2.4.Capacitor Resonance -- 2.3.Resistor Characteristics at High Frequencies -- 2.3.1.High-Frequency Surface Mount Resistors -- 2.3.2.Flip-Chip Surface Mount Resistors -- 2.3.3.Thick-Film and Thin-Film Surface Mount Resistors -- 2.3.4.High-Frequency Effects of Thick-Film and Thin-Film Resistors -- 2.3.5.Notes on Thin-Film Resistors -- 2.3.6.Notes on Thick-Film Resistors -- 2.4.Inductors -- 2.4.1.Calculating Inductance of a Cylindrical Coil of Wire -- 2.4.2.Inductors at High Frequencies -- 2.4.3.Inductors at Resonance -- 2.4.4.Inductance of a Straight Wire -- 2.4.5.Planar Spiral Inductors -- 2.4.6.Conical Inductors -- 2.4.7.Inductance of Via Holes -- 2.4.8.Inductance of Bond Wire -- 2.4.9.Inductance of Flat or Ribbon Wire -- References -- ch. 3 Transmission Lines -- 3.1.Introduction to Transmission Line Theory -- 3.2.Common Transmission Line Topologies

Note continued: 4.3.3.Converting S-Parameters to ABCD Parameters and ABCD Parameters to S-Parameters -- 4.4.S-Parameters of Multiport Networks -- 4.4.1.Example of a Multiport Device: Branch Line Coupler -- 4.5.S-Parameter Summary -- References -- ch. 5 Microstrip Transmission Lines -- 5.1.Microstrip Transmission Lines -- 5.2.Dielectric Material -- 5.3.Effective Conductor Width of a Microstrip Transmission Line -- 5.4.Effective Dielectric Constant in a Microstrip Transmission Line -- 5.5.Wave Velocity and Wavelength of a Signal Traveling Through a Dielectric Material -- 5.6.The Effective Wave Velocity and Wavelength in a Microstrip Transmission Line -- 5.7.Calculating the Impedance of a Microstrip Transmission Line -- 5.8.Calculating the Line Width for a Desired Impedance -- 5.9.Optimizing Bends in Microstrip Transmission Lines -- 5.10.Transmission Line Losses -- 5.10.1.Transmission-Line Conductor Losses -- 5.10.2.Dielectric Material Losses

Note continued: 5.10.3.Summary of Transmission Line Losses -- References -- ch. 6 Circuit Matching and VSWR -- 6.1.Introduction -- 6.2.Maximum Power Transfer -- 6.3.Electromagnetic Waves Traveling Through an Infinite Transmission Line -- 6.3.1.Distributed Attenuation -- 6.3.2.Distributed Delay -- 6.4.Reflected Waves in a Transmission Line -- 6.4.1.Reflections from a Short-Circuit Load Impedance -- 6.4.2.Reflections from an Open-Circuit Load Impedance -- 6.5.Voltage Standing Wave Ratio -- 6.5.1.VSWR as a Function of the Reflection Coefficient -- 6.5.2.Reflection Coefficient as a Function of the VSWR -- 6.5.3.VSWR as a Function of the Source and Load Impedance -- 6.6.Mismatch Loss -- 6.7.Mismatch Uncertainty -- 6.7.1.Amplitude Uncertainty -- 6.7.2.Phase Uncertainty -- 6.7.3.VSWR Uncertainty -- 6.8.Matching Impedances -- 6.8.1.Matching with a Quarter-Wave Transmission Line -- 6.8.2.Using a Matched Resistive Attenuator to Improve VSWR -- References

Note continued: ch. 7 Noise in Microwave Circuits -- 7.1.Introduction -- 7.2.Properties of Noise -- 7.2.1.Thermal Noise -- 7.2.2.Flicker Noise -- 7.2.3.Phase Noise -- 7.3.Noise Figure -- 7.4.Noise Temperature -- 7.5.Modeling the Noise Figure of a Single Amplifier -- 7.6.Noise Figure of Passive Devices -- 7.7.Noise Figure of Cascaded Devices -- 7.7.1.Cascading Two Amplifiers -- 7.7.2.Noise Figure of a Cascade of Multiple Devices -- 7.8.Noise Figure Calculation Example -- References -- ch. 8 Nonlinear Signal Distortion -- 8.1.Introduction -- 8.2.Distortion Originating in the Frequency Domain -- 8.3.Distortion of a Single Sinusoidal Signal Due to Device Nonlinearity -- 8.3.1.Mathematical Representation of a Nonlinear Transfer Function -- 8.3.2.Harmonic Distortion Due a Device Nonlinearity -- 8.3.3.Gain Through a Nonlinear Device -- 8.3.4.Gain Compression -- 8.4.Intermodulation Interference Frequencies -- 8.5.Second-Order Intermodulation Distortion

Note continued: 8.5.1.Levels and Spectrum of Second-Order Intermodulation Products -- 8.5.2.Frequency Spectrum of Second-Order Intermodulation Products When the Carriers Are Closely Spaced -- 8.5.3.Frequency Spectrum of Even-Order Intermodulation Products When the Carriers Are Closely Spaced -- 8.5.4.Second-Order Intercept Point and Second-Order Intermodulation Levels -- 8.5.5.Notes on Even-Order Intermodulation Products and Intercept Points -- 8.6.Third-Order Intermodulation Distortion -- 8.6.1.The Frequency Spectrum of Third-Order Intermodulation Products -- 8.6.2.Calculating the Level of Third-Order Intermodulation Products -- 8.6.3.Determining the Relative Level of IP3 and P1dB -- 8.6.4.Third-Order Intercept Point -- 8.6.5.Relative Level of P1dB with Respect to IP3 -- 8.7.Spectrum of Higher-Order Intermodulation Products -- 8.8.Intermodulation Analysis of Cascaded Devices -- 8.8.1.Calculating the Third-Order Intercept Point of Two Devices in Cascade

Note continued: 8.8.2.Calculating the Third-Order Intercept Point of Multiple Devices in Cascade -- References -- ch. 9 System Cascade and Dynamic Range Analysis -- 9.1.Introduction to Cascade Analysis and Dynamic Range -- 9.2.Minimum Signal Level Limitations -- 9.3.Maximum Signal Level Limitations -- 9.3.1.Continuous-Wave Single Signal Maximum Levels -- 9.3.2.Maximum Level for a Single-Signal Modulated Carrier -- 9.4.A Typical Spurious-Free Dynamic Range Calculation -- 9.4.1.Calculating the Normalized Thermal Noise -- 9.4.2.Third-Order Intermodulation Interference -- 9.4.3.Calculating Spurious-Free Dynamic Range -- 9.5.Dynamic Range Analysis: Example -- 9.6.Out-of-Band Noise Power in a Transmitter: Example -- 9.7.Carrier Triple Beats Interference -- 9.8.Multiple Carrier (N > 3) Interference -- References -- ch. 10 Defining the Output Power Requirements in a Communication Link and Other Wireless Systems -- 10.1.Introduction: Power Amplifier Requirements

Note continued: 10.2.Power Amplifier Requirements in a Wireless Communications Link -- 10.3.Design a Receiver Input to Meet a Required Minimum C/N in a Communications System -- 10.4.Path Loss Calculation -- 10.5.Transmitted Power: Equivalent Isotropic Radiated Power -- 10.5.1.Antenna Gain -- 10.5.2.EIRP -- 10.5.3.Example: Determining Power Amplifier Requirements [Pout(dBm)] -- 10.6.G/T Receiver Comparison Indicator -- 10.7.Power Amplifiers for Radar Systems -- 10.7.1.Radar Equation -- 10.7.2.Radar Power Amplifier Linearity -- References -- ch. 11 Parallel Amplifier Topology Enhancing SSPA Performance -- 11.1.Introduction -- 11.2.Performance of Parallel Amplifiers Using Near-Ideal Perfectly Matched Components -- 11.2.1.Gain Calculation for an Ideal Parallel Amplifier Module -- 11.2.2.Noise Figure Calculation for an Ideal Parallel Amplifier Combiner Module -- 11.2.3.Available Output Power in an Ideal Parallel Amplifier Module

Note continued: 11.2.4.Summary of Parallel Amplifier Combining Using Ideal Devices -- 11.3.VSWR Mismatch Loss -- 11.3.1.Reflection Coefficient -- 11.3.2.Effective VSWR at the Interface of Two Nonideal Devices -- 11.3.3.VSWR as a Function of Source and Load Impedance -- 11.4.Nonideal Power Divider and Power Combiner Losses Effecting Gain, Noise Figure, and Intercept Point -- 11.4.1.Power Divider Losses -- 11.4.2.Power Combiner Losses -- 11.4.3.Power Divider and Combiner Loss Effects on Gain -- 11.5.Losses Due to Amplitude and Phase-Matching Errors in Parallel Channels -- 11.5.1.Vector Summing in the Power Combiner -- 11.5.2.Normalized Signal Power at the Output of the Power Combiner -- 11.5.3.Graphical Analysis of Gain Loss and OIP3 Loss as a Function Parallel Path Mismatch -- 11.6.Mismatch Loss Uncertainty and Phase Uncertainty as a Function of VSWR -- 11.6.1.Magnitude Uncertainty Due to Source and Load Mismatch

Note continued: 11.6.2.Phase Uncertainty Due to Source and Load Mismatch -- 11.7.Example: Application of Parallel Path Systematic and Random Losses to the Performance of the SSPA Output Stage -- 11.7.1.Characteristics of the Devices Used in the Parallel Amplifier Topology -- 11.7.2.Calculating the Fixed Losses Associated with the Parallel Amplifier Topology -- 11.7.3.Calculating the Uncertainty Loss Associated with the Parallel Amplifier Topology -- 11.7.4.Summary of the Analysis of the Parallel Amplifier Topology -- References -- ch. 12 MMIC Amplifier Modules for Use in Parallel Combining Circuits -- 12.1.Introduction -- 12.2.Criteria for Selecting Parallel Amplifier Modules -- 12.2.1.Output Power -- 12.2.2.Gain -- 12.2.3.Equal Gain -- 12.2.4.Input and Output VSWR -- 12.2.5.Frequency Flatness -- 12.2.6.Efficiency -- 12.2.7.Amplifier Stability -- 12.3.Interpreting RF Characteristics of MMIC Power Amplifier Devices Using a Typical Example of Manufacturers' Data

Note continued: 12.4.Primary DC Voltage and Bias for FET-Based MMIC Power Amplifier Devices -- 12.4.1.RF Signal Path -- 12.4.2.Input DC Bias Circuit -- 12.4.3.Output DC Bias Circuit -- 12.4.4.Basic Configuration of an N-Channel Depletion-Mode MESFET -- 12.4.5.Voltage Sequencer -- 12.4.6.Typical Block Diagram of a Depletion-Mode MESFET SSPA Module Bias Voltage Switching Network -- References -- ch. 13 Measuring and Matching the Impedance of High-Power MMIC Amplifier Modules -- 13.1.Introduction -- 13.2.Optimum Impedance Matching -- 13.2.1.Using Isolators to Improve Input and Output Amplifier VSWR -- 13.2.2.Using Quadrature Hybrids for Impedance Matching -- 13.3.Measuring the Impedance of Linear Power Amplifier Modules -- 13.3.1.Measuring S11 and S21 of a Linear Power Amplifier Module -- 13.3.2.Measuring S22 and S12 at the Rated Output of a Power Amplifier Module -- 13.4.Measuring the Impedance of Large Signal Nonlinear Power Amplifiers Using a Network Analyzer

Note continued: 13.5.Load-Pull Impedance Measurements -- 13.5.1.Determining the Optimum Input Impedance Using Load-Pull -- 13.5.2.Determining the Optimum Output Impedance Using Load-Pull -- 13.5.3.Calibration of the Input and Output Match Networks -- 13.6.Load-Pull Measuring System -- 13.7.SSPA Module Impedances -- 13.8.Accuracy of SSPA Module Impedance Measurements -- 13.9.Matching the Impedance of Power Amplifiers -- 13.9.1.Impedance Matching Procedure Using RF/Microwave Simulation Program -- 13.9.2.Using a Smith Chart to Select an Optimum Impedance, Power, and Efficiency -- 13.10.An Example of a Computer Simulation of a Matching Network -- 13.10.1.Computer Simulation Setup -- 13.10.2.Computer-Generated Simulation of Network N -- 13.10.3.Results of the Computer Simulation for Network N -- 13.11.Summary -- References -- ch. 14 Power Dividers and Combiners Used in Parallel Amplifier SSPAs -- 14.1.Introduction -- 14.2.Factors to Consider in Power Divider Selection

Note continued: 14.3.Two-Way Wilkinson Power Dividers -- 14.3.1.An Example of a Computer Simulation of a Wilkinson Power Divider -- 14.3.2.Wilkinson Power Divider: Characteristics Pertinent to Parallel Amplifier SSPA Topologies -- 14.4.Quadrature Power Dividers -- 14.4.1.An Example of a Computer Simulation of a Quadrature Power Divider -- 14.4.2.Quadrature Power Divider Characteristics Pertinent to Parallel Amplifier SSPA Topologies -- 14.5.Higher Order In-Phase (Wilkinson) Power Dividers -- 14.5.1.Three-Way Wilkinson Power Divider -- 14.5.2.Example of a Simulation of a Three-Way Wilkinson Power Divider -- 14.5.3.Example of a Three-Way Wilkinson Power Divider in a Planar Configuration -- 14.5.4.An Example of a Three-Way Wilkinson Power Divider with No Isolation Resistors -- 14.5.5.Higher-Order Wilkinson Power Dividers -- 14.6.Higher-Order Radial and Spatial Power Dividers and Combiners -- 14.6.1.Radial Power Dividers and Combiners

Note continued: 14.6.2.Spatial Power Dividers and Couplers -- 14.7.Higher-Order Corporate Power Dividing and Combining Techniques -- 14.8.Summary of Power Divider and Power Combiner techniques -- References -- ch. 15 Power Amplifier Chain Analysis -- 15.1.Introduction -- 15.2.Example: Chain Analysis of a Linear Power Amplifier System -- 15.2.1.Chain Analysis Spreadsheet for Linear Power Amplifiers -- 15.2.2.Interrupting the Information in the Chain Analysis Spreadsheet in Table 15.1 Relating to a Linear Power SSPA -- 15.2.3.Output Power Degradation in a Linear Power Amplifier Chain -- 15.2.4.The Cumulative Effect of Intermodulation Distortion Through the SSPA Chain of Devices on the Available Output Power -- 15.3.The Effect of N Parallel Stages on the Intermodulation Distortion in a Linear SSPA -- 15.3.1.Example: Output Parallel Power Amplifier Third-Order Intermodulation Interference in a Linear SSPA with N Parallel Amplifiers

Note continued: 15.3.2.Other Parameters Affecting the Output Third-Order Intermodulation Interference and Available Output Power -- 15.3.3.A Summary of Some Design Practices Concerning Intermodulation Interference -- 15.4.Chain Analysis of a Saturated Power Amplifier System -- 15.4.1.Example of a Chain Analysis Spreadsheet for Saturated Power Amplifiers -- 15.4.2.Interrupting the Information in the Chain Analysis Spreadsheet in Table 15.6 Relating to a Saturated SSPA -- 15.5.Example: Parasitic Issues Associated with the Parallel High-Power Output Amplifiers -- 15.5.1.Output Combiner Loss -- 15.5.2.Phase-Amplitude Parallel Channel Matching Loss -- 15.5.3.VSWR Mismatch Loss and Phase and Amplitude Uncertainty -- 15.6.Summary of Losses in an N Parallel Amplifier SSPA -- References -- ch. 16 RF Signal Monitoring Circuits -- 16.1.Introduction -- 16.2.Monitoring RF/Microwave Power Levels at Critical Interfaces

Note continued: 16.3.RF/Microwave Bidirectional Coupler for Forward and Reverse Power Sampling -- 16.3.1.Example of a Typical Bidirectional Coupler Used for an SSPA -- 16.3.2.Example: A Computer Simulation of a 1-GHz to 2-GHz Bidirectional Coupler -- 16.3.3.Summary of the Bidirectional Coupler Function and Example -- 16.4.RF/Microwave Signal Power Level Detection -- 16.4.1.Root Mean Square Power -- 16.4.2.Thermistor-Based Power Meters -- 16.4.3.Peak Power Detectors -- 16.4.4.RMS Power Detectors -- References -- ch. 17 DC Power Interface with the RF Signal Path -- 17.1.Introduction -- 17.2.Power Amplifier Circuits Using Depletion-Mode FETs -- 17.3.DC Bias for the Depletion Mode FETs -- 17.3.1.Gate Voltage (Vg) -- 17.3.2.Drain Voltage (Vd) and Drain Current (Id) -- 17.3.3.Gate and Drain Voltage Sequencing -- 17.4.Selection of DC Bias Capacitors -- 17.4.1.Coupling (Series) Capacitors and Decoupling (Shunt) Capacitors -- 17.4.2.Capacitor RF Model

Note continued: 17.4.3.Capacitance Resonance and the Applicable Frequency Range -- 17.5.Selection of DC Bias Inductors -- 17.5.1.Inductor RF Model -- 17.5.2.Inductor Resonance and the Applicable Frequency Range -- 17.5.3.Rated Current of an Inductor -- 17.6.Quarter-Wave Transmission Lines to Bias Power Amplifier Modules -- References -- ch. 18 SSPA DC Voltage and Current -- 18.1.Introduction -- 18.2.DC Power Requirements for a Typical SSPA -- 18.2.1.DC in a Linear (Class AB) Mode SSPA -- 18.2.2.DC in a Saturated Mode SSPA -- 18.2.3.Power Requirements of Depletion-Mode FET -- 18.3.Example: Power Requirements of Each Module in the SSPA Chain -- 18.3.1.DC Power Requirements of the Preamplifier -- 18.3.2.DC Power Requirements of the Driver Amplifier -- 18.3.3.DC Power Requirements of the Output Parallel Amplifier -- 18.3.4.DC Power Requirements and Efficiency of the SSPA (Preamplifier, Drive Amplifier, and Output Parallel Amplifier Combined)

Note continued: 18.4.Meeting the Drain Current Requirements for a Pulsed Saturated Mode SSPA -- 18.4.1.A Drain Voltage and Current Charging and Discharging Model -- 18.4.2.Charging and Discharging the Reservoir Capacitor (Cc) -- 18.5.Example of Changes in Drain Voltage When the Reservoir Capacitor Charges and Discharges -- 18.5.1.Initial Turn-On -- 18.5.2.The Drain Voltage Transient Before, During, and After the RF Pulse -- 18.5.3.Voltage Increase When Between RF Pulses -- 18.5.4.Notes on the Model Used in this Example -- 18.6.Notes on SSPA DC Voltage, Current, and Efficiency -- 18.6.1.General Comments on SSPA Efficiency -- 18.6.2.Notes on the Efficiency of SSPAs Operated in a Saturated Pulse Mode -- 18.6.3.Efficiency of CW Communications Amplifiers -- References -- ch. 19 Thermal Design and Reliability -- 19.1.Introduction -- 19.2.Device Reliability as a Function of Temperature -- 19.2.1.Accelerated Life Test -- 19.2.2.Determining MTTF from Accelerated Life Test Data

Note continued: 19.2.3.Example: Using Accelerated Life Test Data to Determine MTTF -- 19.2.4.Notes on Device Reliability as a Function of Temperature -- 19.3.Calculating the Power Dissipation and Temperature Rise in an FET Amplifier Module -- 19.3.1.FET Channel to Case Temperature Differential -- 19.3.2.FET Channel to Ambient Temperature Differential -- 19.3.3.Thermal Model of an FET Amplifier Module -- 19.3.4.Techniques to Reduce the Thermal Resistance Between the FET Channel and the Ambient Temperature -- 19.4.Examples of FET Power Amplifier Module Thermal Calculations -- 19.4.1.Example: Calculating FET Channel Temperature -- 19.4.2.Example: Calculating FET Channel Temperatures Through Multiple Thermal Paths -- 19.5.Thermal Transients -- 19.5.1.DC Power Turn-On Thermal Transients in Linear and CW-Mode SSPAs -- 19.5.2.Implications of Thermal Transients in the Design of a Pulse Saturated Mode SSPA

Note continued: 19.5.3.Example: Maximum FET Channel Temperature as a Function of RF Pulse Width -- 19.6.Conclusions -- References -- ch. 20 Electromagnetic Interference -- 20.1.Introduction -- 20.2.The Concept of Electromagnetic Compatibility -- 20.3.Mutual Coupling and Crosstalk on a Printed Circuit Board -- 20.3.1.Capacitive Coupling -- 20.3.2.Inductive Coupling -- 20.3.3.Crosstalk -- 20.4.Far-Field Radiated Emissions and Radiated Susceptibility -- 20.4.1.Far-Field Approximation -- 20.4.2.Chassis Shielding -- 20.4.3.Chassis and Wall Thickness -- 20.4.4.Radiation Through Chassis Openings -- 20.4.5.Radiation Through Chassis Covers -- 20.4.6.Limitations on Chassis Walls and Cover Separation from the Signal Path -- 20.4.7.Notes on Radiated Emissions and Radiated Susceptibility -- 20.5.Conducted Emissions and Conducted Susceptibility -- 20.5.1.Conducted Emission and Susceptibility on Signal Lines -- 20.5.2.Conducted Emission and Susceptibility on DC Power Lines

Note continued: 20.6.DC Power-Line Filtering -- 20.6.1.Wideband Power Line Filtering (Area #1) -- 20.6.2.Notes on Wideband Power-Line Filtering -- 20.7.DC-DC Converter Efficiency and Effect on Spurious Emissions -- 20.7.1.Regulator Efficiency -- 20.7.2.Conflicting Requirements Designing a DC-to-DC Converter -- References.