VLSI-design of non-volatile memories / Giovanni Campardo, Rino Micheloni, David Novosel.
Material type:
TextPublisher: Berlin ; New York : Springer, [2005]Copyright date: ©2005Description: xxviii, 581 pages : illustrations ; 24 cmContent type: - text
- unmediated
- volume
- 9788181288073
- 354020198x
- Very large scale integrated design of non-volatile memories
- 621.395 C.G.V 22
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | |
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Main library B3 | Faculty of Engineering & Technology (Electrical) | 621.395 C.G.V (Browse shelf(Opens below)) | Available | 00011001 | ||
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Books
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Main library B3 | Faculty of Engineering & Technology (Electrical) | 621.395 C.G.V (Browse shelf(Opens below)) | Available | 00005248 |
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| 621.395 B.S.F Fundamentals of digital logic with VHDL design / | 621.395 C.D.D Digital logic and state machine design / | 621.395 C.G.V VLSI-design of non-volatile memories / | 621.395 C.G.V VLSI-design of non-volatile memories / | 621.395 D.D.V VHDL : design, synthesis, and simulation / | 621.395 G.D.F Fundamentals of VLSI design / | 621.395 G.D.P. Principles of digital design / |
Includes bibliographical references and index.
Non-Volatile Memory Design -- Process Aspects -- The MOSFET Transistor and the Memory Cell -- Passive Components -- Fundamental Circuit Blocks -- The Organization of the Memory Array -- The Input Buffer – Decoders – Boost -- Synchronization Circuits -- Reading Circuits -- Multilevel Read -- Program and Erase Algorithms -- Circuits Used in Program and Erase Operations -- High-Voltage Management System -- Program and Erase Controller -- Redundancy and Error Correction Codes -- The Output Buffer -- Test Modes -- ESD & Latch-Up -- From Specification Analysis to Floorplan Definition -- Photo Album
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