TY  - BOOK
AU  - Kang,Sung-Mo
AU  - Leblebici,Yusuf
TI  - CMOS digital integrated circuits: analysis and design 
SN  - 0072925078
U1  - 621.395 21
PY  - 1998///]
CY  - Boston, MA
PB  - McGraw-Hill
KW  - Metal oxide semiconductors, Complementary
KW  - Digital integrated circuits
N1  - Includes bibliographical references and index; ch. 1 Introduction -- 1.1. Historical Perspective -- 1.2. Objective and Organization of the Book -- 1.3. A Circuit Design Example -- ch. 2 Fabrication of MOSFETs -- 2.1. Introduction -- 2.2. Fabrication Process Flow: Basic Steps -- 2.3. The CMOS n-Well Process -- 2.4. Layout Design Rules -- 2.5. Full-Custom Layout Design Rules --  ch. 3 MOS Transistor -- 3.1. The Metal Oxide Semiconductor (MOS) Structure -- 3.2. The MOS System Under External Bias -- 3.3. Structure and Operation of the MOS Transistor (MOSFET) -- 3.4. MOSFET Current-Voltage Characteristics -- 3.5. MOSFET Scaling and Small-Geometry Effects -- 3.6. MOSFET Capacitances -- ch. 4 Modelling of MOS Transistors Using SPICE -- 4.1. Basic Concepts -- 4.2. The Level 1 Model Equations -- 4.3. The Level 2 Model Equations -- 4.4. The Level 3 Model Equations -- 4.5. Capacitance Models -- 4.6. Comparison of the SPICE MOSFET Models -- ch. 5 MOS Inverters: Static Characteristics -- 5.1. Introduction -- 5.2. Resistive-Load Inverter -- 5.3. Inverters with MOSFET Load -- 5.4. CMOS Inverter -- ch. 6 MOS Inverters: Switching Characteristics and Interconnect Effects -- 6.1. Introduction -- 6.2. Delay-Time Definitions --6.3. Calculation of Delay Times -- 6.4. Inverter Design with Delay Constraints -- 6.5. Estimation of Interconnect Parasitics -- 6.6. Calculation of Interconnect Delay -- 6.7. Switching Power Dissipation of CMOS Inverters -- ch. 7 Combinational MOS Logic Circuits -- 7.1. Introduction -- 7.2. MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads -- 7.3. CMOS Logic Circuits -- 7.4. Complex Logic Circuits -- 7.5. CMOS Transmission Gates (Pass Gates) -- ch. 8 Sequential MOS Logic Circuits --
8.1. Introduction -- 8.2. Behaviour of Bistable Elements -- 8.3. The SR Latch Circuit -- 8.4. Clocked Latch and Flip-Flop Circuits -- 8.5. CMOS D-Latch and Edge-Triggered Flip-Hop -- ch. 9 Dynamic Logic Circuits -- 9.1. Introduction --
9.2. Basic Principles of Pass Transistor Circuits -- 9.3. Voltage Bootstrapping -- 9.4. Synchronous Dynamic Circuit Techniques -- 9.6. High-Performance Dynamic CMOS Circuits --

UR  - http://www.loc.gov/catdir/description/mh023/98028075.html
UR  - http://www.loc.gov/catdir/toc/mh022/98028075.html
ER  -