000			01786cam a2200349 i 4500
999			_c12000 _d12000
001			15141403
005			20210222113421.0
008			080114s2018 ii a 001 0 eng
010			_a 2008001634
020			_a9780198093299
020			_a0198093292
040			_aDLC _cDLC _dUKM _dBTCTA _dYDXCP _dBAKER _dBWX _dCOD _dIXA _dDLC _erda
050	0	0	_aTK7888.4 _b.B76 2008
082	0	0	_a621.395 _223 _bD.D.V
100	1		_aDas, Debaprasad. _eauthor.
245	1	0	_aVHDL : _bdesign, synthesis, and simulation / _cDebaprasad Das.
264		1	_aNew Delhi : _bOxford University Press, _c[2018]
264		4	_c©2018
300			_axviii, 588 pages : _billustrations ; _c22 cm
336			_2rdacontent _atext
337			_2rdamedia _aunmediated
338			_2rdacarrier _avolume
500			_aIncludes index.
505	0		_aIntroduction to Digital Logic Design Introduction to VHDL -- Dataflow Modeling -- Behavioral Modeling -- Structural Modeling -- Mixed Modeling -- Concurrent Statements -- Sequential Statements -- Advanced VHDL -- Arithmetic Logic Unit Design -- Model Simulation -- Delay Modeling -- Verification and Testing -- Synthesis -- Place and Route -- File I/O -- Floating-point Arithmetic -- Design with FPGA and CPLD -- Memories and Buses -- Design Examples -- Introduction to Verilog
538			_aMinimum system requirements (PC): Pentium III processor or later; Windows XP or later; USB port for connecting a USB-Blaster; TCP/IP networking protocol installed; Internet Explorer 6.0 or later.
650		0	_aLogic circuits _xDesign and construction _xData processing. _926019
650		0	_aLogic design _xData processing. _926020
650		0	_aVHDL (Computer hardware description language) _926021
942			_cBK _2ddc