000			03775nam a2200325 i 4500
999			_c2413 _d2413
001			2104586
005			20210222115045.0
008			960118s1997 njua f b 001 0 eng d
010			_a 96001339
020			_a0133011445
040			_aDLC _cDLC _dDLC _erda
082	0	0	_a621.395 _220 _bG.D.P.
100	1		_aGajski, Daniel D. _99947 _eauthor.
245	1	0	_aPrinciples of digital design / _cDaniel D. Gajski.
264		1	_aUpper Saddle River, N.J. : _bPrentice Hall, _c[1997]
264		4	_c©1997
300			_axv, 447 pages : _billustrations (some color) ; _c24 cm
336			_2rdacontent _atext
337			_2rdamedia _aunmediated
338			_2rdacarrier _avolume
504			_aIncludes bibliographical references and index.
505	0		_a1.Introduction -- Design representation -- Levels of abstraction -- Design process -- CAD tools -- Typical design process -- Road map – 2. Data Types and Representations -- Positional number systems -- Octal and hexadecimal numbers -- Number system conversions -- Addition and subtraction of binary numbers -- Representation of negative numbers -- Two's-complement addition and subtraction -- Binary ultiplication -- Binary division -- Floating-point number representation -- Binary codes for decimal numbers -- Character codes -- Codes for error detection and correction -- Hamming codes – 3. Boolean Algebra and Logic Design -- Algebraic properties -- Axiomatic definition of boolean algebra -- Basic theorems of boolean algebra -- Boolean functions -- Canonical forms -- Standard forms -- Digital logic gates -- Extension to multiple inputs and multiple operators -- Gate implementations -- VLSI technology – 4. Simplification of Boolean Functions -- The map representation -- The map method of simplification -- Don't-care conditions -- The tabulation method -- Technology mapping for gate arrays -- Technology mapping for custom libraries -- Hazard-free design – 5. Combinatorial Components -- Carry-ripple adders -- Carry-look-ahead adders -- Adders/subtractors -- Logic unit -- Arithmetic-Logic Unit -- Decoders -- Selectors -- Buses -- Priority encoders -- Magnitude comparators -- Shifters and rotators -- Read-Only memories -- Programmable logic arrays – 6. Sequential Logic -- SR-latch -- Gated SR-latch -- Gated D-latch -- Flip-flops -- Flip-flop types -- Analysis of sequential logic -- Finite-state-machine model -- Synthesis of sequential logic -- FSM model capture -- State minimization -- State encoding -- Choice of memory elements -- Optimization and timing – 7. Storage Components -- Registers -- Shift registers -- Counters -- BCD counter -- Asynchronous counter -- Register files -- Random-access memories (RAMs) -- Push-down stacks -- Firs- in-first-out queue -- Simple datapaths -- General datapaths -- Control unit design – 8. Register-Transfer Design -- Design model -- FSMD definition -- Algorithmic-state-machine charts -- Synthesis from ASM charts -- Register sharing (variable merging) -- Functional unit sharing (operator sharing) -- Bus sharing (connection merging) -- Register merging -- Chaining and multicycling -- Functional unit pipelining -- ASM pipelining -- Control- pipelining -- Scheduling – 9.Processor Design -- Instruction sets -- Addressing modes -- Processor design -- Instruction set design -- Processor design -- Reduced instruction set -- RISC Design -- Data forwarding -- Branch prediction.
650		0	_aIntegrated circuits _xDesign _xData processing.
650		0	_aLogic design _xData processing.
650		0	_aComputer-aided design.
906			_a7 _bcbc _corignew _d1 _eocip _f19 _gy-gencatlg
942			_2ddc _cBK