| 000 | 02080nam a2200361 i 4500 | ||
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| 999 |
_c2417 _d2417 |
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| 001 | 4047923 | ||
| 005 | 20210222103213.0 | ||
| 008 | 990113s1999 maua f 001 0 eng d | ||
| 010 | _a 99017750 | ||
| 020 | _a0792384741 (alk. paper) | ||
| 040 |
_aDLC _cDLC _dDLC _erda |
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| 082 | 0 | 0 |
_a621.392 _221 _bC.B.V. |
| 100 | 1 |
_aCohen, Ben, _d1945-, _99962 _eauthor. |
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| 245 | 1 | 0 |
_aVHDL coding styles and methodologies / _cBen Cohen. |
| 250 | _aSecond edition | ||
| 264 | 1 |
_aBoston : _bKluwer Academic Publishers, _c[1999] |
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| 264 | 4 | _c©1999 | |
| 300 |
_axviii, 453 pages : _billustrations ; _c27 cm |
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| 336 |
_2rdacontent _atext |
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| 337 |
_2rdamedia _aunmediated |
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| 338 |
_2rdacarrier _avolume |
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| 500 | _a"...an in-depth tutorial"--Cover. | ||
| 500 | _aIncludes index. | ||
| 505 | 0 | _aPreface -- VHDL Overview and Concepts -- Basic Language Elements -- Control Structures -- Drivers -- VHDL Timing -- Elements of Entity/Architecture -- Subprograms -- Packages -- User Defined Attributes, Specifications, and Configurations -- Design for Synthesis -- Functional Models and Testbenches -- UART Project -- Appendix A: VHDL 93 and VHDL 87 Syntax Summary -- Appendix B: Package Standard -- Appendix C: Package Textio -- Appendix D: STD_Logic_Textio -- Appendix E: Package STD_Logic_1164 -- Appendix F: Numeric_STD -- Appendix G: STD_Logic_Unsigned -- Appendix H: STD_Logic_Signed -- Appendix I: STD_Logic_Arith -- Appendix J: STD_Logic_Misc -- Appendix K: VHDL Predefined Attributes -- Index. | |
| 650 | 0 | _aVHDL (Computer hardware description language) | |
| 856 | 4 | 2 |
_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0820/99017750-d.html |
| 856 | 4 | 1 |
_3Table of contents only _uhttp://www.loc.gov/catdir/enhancements/fy0820/99017750-t.html |
| 856 | 4 | 1 |
_3Abstract _uhttp://repository.fue.edu.eg/xmlui/handle/123456789/3878 |
| 906 |
_a7 _bcbc _corignew _d1 _eocip _f19 _gy-gencatlg |
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| 942 |
_2ddc _cBK |
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