VHDL : design, synthesis, and simulation / Debaprasad Das.

By:

Das, Debaprasad [author.]

Material type: Text

text

Media type:

unmediated

Carrier type:

volume

ISBN:

9780198093299
0198093292

Subject(s):

DDC classification:

621.395 23 D.D.V

LOC classification:

TK7888.4 .B76 2008

Contents:

Introduction to Digital Logic Design Introduction to VHDL -- Dataflow Modeling -- Behavioral Modeling -- Structural Modeling -- Mixed Modeling -- Concurrent Statements -- Sequential Statements -- Advanced VHDL -- Arithmetic Logic Unit Design -- Model Simulation -- Delay Modeling -- Verification and Testing -- Synthesis -- Place and Route -- File I/O -- Floating-point Arithmetic -- Design with FPGA and CPLD -- Memories and Buses -- Design Examples -- Introduction to Verilog

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Item type	Current library	Collection	Call number	Copy number	Status	Date due	Barcode
Books	Main library B3	Faculty of Engineering & Technology (Electrical)	621.395 D.D.V (Browse shelf(Opens below))	1	Available		00015420

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Includes index.

Introduction to Digital Logic Design
Introduction to VHDL -- Dataflow Modeling -- Behavioral Modeling -- Structural Modeling -- Mixed Modeling -- Concurrent Statements -- Sequential Statements -- Advanced VHDL -- Arithmetic Logic Unit Design -- Model Simulation -- Delay Modeling -- Verification and Testing -- Synthesis -- Place and Route -- File I/O -- Floating-point Arithmetic -- Design with FPGA and CPLD -- Memories and Buses -- Design Examples -- Introduction to Verilog

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