Ramdan Hours:
Sun - Thu
9.30 AM - 2.30 PM
Iftar in --:--:--
🌙 Maghrib: --:--
Image from Google Jackets

CMOS digital integrated circuits : analysis and design / Sung-Mo (Steve) Kang, Yusuf Leblebici.

By: Contributor(s): Material type: TextTextPublisher: Boston, MA : McGraw-Hill, [1998]Copyright date: ©1999Edition: Second editionDescription: xv, 658 pages : illustrations ; 25 cmContent type:
  • text
Media type:
  • unmediated
Carrier type:
  • volume
ISBN:
  • 0072925078
Subject(s): DDC classification:
  • 621.395 21 K.S.C.
Online resources:
Contents:
ch. 1 Introduction -- 1.1. Historical Perspective -- 1.2. Objective and Organization of the Book -- 1.3. A Circuit Design Example -- ch. 2 Fabrication of MOSFETs -- 2.1. Introduction -- 2.2. Fabrication Process Flow: Basic Steps -- 2.3. The CMOS n-Well Process -- 2.4. Layout Design Rules -- 2.5. Full-Custom Layout Design Rules -- ch. 3 MOS Transistor -- 3.1. The Metal Oxide Semiconductor (MOS) Structure -- 3.2. The MOS System Under External Bias -- 3.3. Structure and Operation of the MOS Transistor (MOSFET) -- 3.4. MOSFET Current-Voltage Characteristics -- 3.5. MOSFET Scaling and Small-Geometry Effects -- 3.6. MOSFET Capacitances -- ch. 4 Modelling of MOS Transistors Using SPICE -- 4.1. Basic Concepts -- 4.2. The Level 1 Model Equations -- 4.3. The Level 2 Model Equations -- 4.4. The Level 3 Model Equations -- 4.5. Capacitance Models -- 4.6. Comparison of the SPICE MOSFET Models -- ch. 5 MOS Inverters: Static Characteristics -- 5.1. Introduction -- 5.2. Resistive-Load Inverter -- 5.3. Inverters with MOSFET Load -- 5.4. CMOS Inverter -- ch. 6 MOS Inverters: Switching Characteristics and Interconnect Effects -- 6.1. Introduction -- 6.2. Delay-Time Definitions --6.3. Calculation of Delay Times -- 6.4. Inverter Design with Delay Constraints -- 6.5. Estimation of Interconnect Parasitics -- 6.6. Calculation of Interconnect Delay -- 6.7. Switching Power Dissipation of CMOS Inverters -- ch. 7 Combinational MOS Logic Circuits -- 7.1. Introduction -- 7.2. MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads -- 7.3. CMOS Logic Circuits -- 7.4. Complex Logic Circuits -- 7.5. CMOS Transmission Gates (Pass Gates) -- ch. 8 Sequential MOS Logic Circuits -- 8.1. Introduction -- 8.2. Behaviour of Bistable Elements -- 8.3. The SR Latch Circuit -- 8.4. Clocked Latch and Flip-Flop Circuits -- 8.5. CMOS D-Latch and Edge-Triggered Flip-Hop -- ch. 9 Dynamic Logic Circuits -- 9.1. Introduction -- 9.2. Basic Principles of Pass Transistor Circuits -- 9.3. Voltage Bootstrapping -- 9.4. Synchronous Dynamic Circuit Techniques -- 9.6. High-Performance Dynamic CMOS Circuits --
Star ratings
    Average rating: 0.0 (0 votes)
Holdings
Item type Current library Collection Call number Status Date due Barcode
Books Books Main library B3 Faculty of Engineering & Technology (Electrical) 621.395 K.S.C. (Browse shelf(Opens below)) Available 00007262
Books Books Main library B3 Faculty of Engineering & Technology (Electrical) 621.395 K.S.C. (Browse shelf(Opens below)) Available 00007264
Books Books Main library B3 Faculty of Engineering & Technology (Electrical) 621.395 K.S.C. (Browse shelf(Opens below)) Available 00007263

Includes bibliographical references and index.

ch. 1 Introduction -- 1.1. Historical Perspective -- 1.2. Objective and Organization of the Book -- 1.3. A Circuit Design Example -- ch. 2 Fabrication of MOSFETs -- 2.1. Introduction -- 2.2. Fabrication Process Flow: Basic Steps -- 2.3. The CMOS n-Well Process -- 2.4. Layout Design Rules -- 2.5. Full-Custom Layout Design Rules -- ch. 3 MOS Transistor -- 3.1. The Metal Oxide Semiconductor (MOS) Structure -- 3.2. The MOS System Under External Bias -- 3.3. Structure and Operation of the MOS Transistor (MOSFET) -- 3.4. MOSFET Current-Voltage Characteristics -- 3.5. MOSFET Scaling and Small-Geometry Effects -- 3.6. MOSFET Capacitances -- ch. 4 Modelling of MOS Transistors Using SPICE -- 4.1. Basic Concepts -- 4.2. The Level 1 Model Equations -- 4.3. The Level 2 Model Equations -- 4.4. The Level 3 Model Equations -- 4.5. Capacitance Models -- 4.6. Comparison of the SPICE MOSFET Models -- ch. 5 MOS Inverters: Static Characteristics -- 5.1. Introduction -- 5.2. Resistive-Load Inverter -- 5.3. Inverters with MOSFET Load -- 5.4. CMOS Inverter -- ch. 6 MOS Inverters: Switching Characteristics and Interconnect Effects -- 6.1. Introduction -- 6.2. Delay-Time Definitions --6.3. Calculation of Delay Times -- 6.4. Inverter Design with Delay Constraints -- 6.5. Estimation of Interconnect Parasitics -- 6.6. Calculation of Interconnect Delay -- 6.7. Switching Power Dissipation of CMOS Inverters -- ch. 7 Combinational MOS Logic Circuits -- 7.1. Introduction -- 7.2. MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads -- 7.3. CMOS Logic Circuits -- 7.4. Complex Logic Circuits -- 7.5. CMOS Transmission Gates (Pass Gates) -- ch. 8 Sequential MOS Logic Circuits --
8.1. Introduction -- 8.2. Behaviour of Bistable Elements -- 8.3. The SR Latch Circuit -- 8.4. Clocked Latch and Flip-Flop Circuits -- 8.5. CMOS D-Latch and Edge-Triggered Flip-Hop -- ch. 9 Dynamic Logic Circuits -- 9.1. Introduction --
9.2. Basic Principles of Pass Transistor Circuits -- 9.3. Voltage Bootstrapping -- 9.4. Synchronous Dynamic Circuit Techniques -- 9.6. High-Performance Dynamic CMOS Circuits --

There are no comments on this title.

to post a comment.